IEEE 1394 (Firewire) High Speed Serial Bus

by devnull

  • Overview
  • IEEE 1394 Standard Description
  • Physical Layer
    • Bus Configuration
    • Normal Arbitration
  • Link Layer
  • Transaction Layer
  • Bus Management
  • Software


The IEEE 1394 bus was proposed as a fast, cheap and easy to use serial bus to interconnect computers and peripheral devices. Although it started off as a computer-related interconnection standard, it was adopted by consumer electronics manufacturers as the means to connect numerous digital consumer devices in order to drive the convergence between home electronic appliances and computers. This resulted in a standardization of the technology by IEEE in the mid-90s under the name IEEE 1394-1995. The name Firewire by which the standard is widely known, is Apple's trademarked name of its implementation.

The basic principle behind the design of the standard, is to provide a low-cost high-performance interconnection bus between electronic devices with plug and play capabilities and easy expandability. As a result, the standard's concept is to form a peer-to-peer network, with every connected device being an equal node (meaning that the presence of a central host is not required) while the topology may be changing dynamically as devices are added or removed from the network (dynamic plug'n'play, auto bus configuration). In order to respond to the requirements of the different devices that could be connected through the bus (e.g. audio/video devices, storage units, computer peripherals etc), the IEEE 1394 standard offers high speed data transfers of 100, 200 and 400Mbit/s and two basic ways to transfer information between connected devices : isochronous and asychronous transfers.

Isochronous transfers are used by applications that require guaranteed time delay, while there is tolerance in the validity of data. Video streams are an example of such an application. On the contrary, asychronous transfers are used to transfer control information or data whose correctness must be guaranteed but there can be some flexibility concerning the delivery time (a typical application of this type is the data transfer between storage devices).

Officially the standard is described by the IEEE 1394-1995 specification. This spec defines 3 basic data rates of 100, 200 and 400 Mbit/s. In the beginning of the deployment of the standard, a number of implementation parameters were left to the discretion of the manufacturers. This resulted in some compatibility problems between devices using implementations of different manufacturers and eventually the specification was revised in 2000, to form the IEEE 1394a specification. The revision of the standard provided a much stricter specification and added a number of characteristics to improve the efficiency of the bus. Since then, another update of the standard has been made (1394b) that raises the maximum transfer rate to 800 Mbit/s and there is ongoing work to raise it even further (to 1600 and 3200 Mbit/s), to support transfers to greater distances over twisted-pair cables and optical fiber, while retaining backwards compatibility.

IEEE 1394 Standard Description

The 1394 protocol is a peer-to-peer network. Every node of the network is a device equipped with the necessary functionality to perform configuration and control actions. Each network node may have multiple ports that act as a repeater. That means that packets received on some port of a node are forwarded to all other ports of the same node.

The following figure (Figure 1) demonstrates a possible 1394 network of home appliances.

A 1394 network
Figure 1.

Since 1394 is a peer-to-peer protocol, the existence of a central host on the bus is not required. Every device that supports the 1394 protocol can forward data to any other device of the network.

The maximum number of devices on the bus is 63. According to the spec P1394.1 if there is a need to add more devices, then bridges can be used, raising the total number of supported connected devices on a 1394 network to 65536 (64 nodes on each bus and up to 1024 buses). The devices on the bus are connected on a daisy chain manner, which removes the need of hub-like devices like the ones found on typical Ethernet or USB networks. The formation of cycles is not permitted though. Every node on the network with 2 or more ports forwards all the traffic it receives and as a result each node that participates on the network is exposed to all the traffic of the bus.

Bus configuration is performed automatically whenever a new device is connected. The goal of the configuration is to form a logical tree. The procedure starts from the leaf-nodes, i.e. the devices that are connected to only one other device, and moves on to the neighbooring nodes. On a bus that connects three or more devices, a node will eventually be selected to be configured as the root-node of the network. In short, this root-node will have to generate a number of signals for the synchronization of the devices on the bus and the arbitration of the bus accesses.

A 1394 bus appears as a large memory-mapped space with every connected device having a specific address space. The memory space is based on the IEEE 1212 Control and Status Register architecture with certain extensions specifically for the 1394 standard. Each node supports 48 bits address space (256 TeraBytes). As already mentioned, each bus can support up to 64 nodes and in total the 1394 standard supports up to 1024 buses, resulting in a total address space of 64 bits or 16 ExaBytes of memory space.

Data transfers between connected devices can be realised in two ways : isochronous or asychronous. Isochronous transfers are always broadcast with either a transmitter and a single receiver or a transmitter and numerous receivers. During an isochronous transfer no error correction or retransmission is performed. Up to 80% of the available bandwidth can be used for this kind of transfers. The distribution of bandwidth among the different devices is defined by a node that undertakes the role of the Isochronous Resource Manager (IRM). Therefore, the maximum percentage of bandwidth that can be devoted to a single device on the network is limited by the number of the connected devices to which the IRM has already granted bandwidth.

Asychronous transfers, on the other hand, are not broadcasted but always target a specific network node using an explicit address. These transfers do not have a guaranteed bandwidth on the bus, but when asychronous transfers are allowed, fair access on the bus is provided. For each asychronous transfer, there is always confirmation for the integrity of data sent from the receiver to the transmitter. This allows error corrections and establishes retransmission mechanisms.

The 1394 standard defines 4 layers of protocols, the physical layer, the link layer, the transaction layer and the serial bus management layer. Figure 2 presents the protocol stack of the 1394 standard.

1394 protocol stack
Figure 2.

The physical layer is located at the bottom of the stack and it is the part of the standard that provides the electrical and mechanical interfaces to the bus, enabling the transfer of data packets. Furthermore, bus arbitration and configuration is performed at this level. It is implemented in hardware and usually at the form of a single chip (although there are numerous implementations that integrate the physical and link layers on the same chip).

The link layer is responsible for the assembling and disassembling of the data packets, the error control and the forwarding of packets to the correspoding protocol layers. Packet ackwoledgments and replies are also handled by this layer.

The transaction layer is associated with the asychronous packet transfers. It is implemented mostly in software just like the serial bus management layer. The latter performs tasks that extend to more than one node of the network and are related to the synchronization of the bus, the resources distribution and in general the administration of the bus.

Beyond these defined layers of the 1394 standard, there is an application layer that is located on top of the predescribed protocol stack and it is the layer that is exposed to the user. Because of the variety of the devices that the 1394 bus is used to connect, a great number of application layers has been developped. These implementations normally fit in one of two categories : protocols that are related to consumer devices and protocols related to computers. Only a part of these protocols is presented in Figure 3, which indicates how many have been developped.

Application layer protocols
Figure 3.

On Figure 3, the various protocols are grouped into the two categories that have been mentioned. For example, in computer-related protocols one may find protocols concerning drivers for 1394 pc cards (Open Host Controller Interface) or for TCP/IP networking over 1394 (IP over 1394). On the other hand, protocols like DV (Digital Video) or AV/C (Audio Video / Command) are used for the interconnection of audiovisual consumer devices.

Physical Layer

The physical layer of the 1394 protocol defines the electrical signals, the mechanical connectors and the wiring, the arbitration mechanisms and the serial coding and decoding of transmitting or receiving data.

The cable media is defined as a three-pair shielded cable. Two pairs are used for data transfers, while the third one provides power on the bus. The connectors used are small 6-pin devices. In the 1394a revision, smaller connectors with 4 pins for energy-autonomous devices are also defined (the pins that are not included are the power pins). These devices however can only be configured as leaf-nodes in the 1394 tree. The length of baseline cables is limited to 4.5 meters. Thicker cables to allow greater lengths are also available.

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki
Figure 4.

The twisted pairs used to transmit data (named TPA and TPB), are bidirectional and tri-state capable. TPA is used to transmit the strobe signal and receive data, while the TPB is used to receive the strobe signal and transmit data. No specific line is used to carry a dedicated timing signal. For the synchronization of the devices on the bus the data strobe encoding technique is used. According to this technique, the extraction of the clock signal is realised through the serial data and the strobe signal which results in increased jitter tolerance compared to a standard clock/data mechanism. More specifically, during a bit cell, either the data or the strobe signal change (but not both) and the clock may be extracted by applying the logic-XOR between data and strobe singal, as indicated in Figure 5.

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki
Figure 5.

The physical layer plays a key role in the bus configuration and arbitration phases as defined by the 1396 standard. The bus configuration process forms a logical tree structure with one root node from the flat physical topology. The bus is reset and reconfigured each time a new device is added or removed. The reset process may also by initiated by software. Bus configuration process consists of three phases :

1. Bus reset and initialization : reset is signaled by a node that drives both TPA and PTB lines at logical 1. Because of the electrical specifications of the drivers used, a logical 1 is always identified by a port, even when the bidirectional driver of that port is in a transmission state. When a node detects a reset condition on its drivers, then this signal will be forwarded to all its ports. After that, the node will enter an idle state for a predefined time interval, so that the reset signal reaches all network nodes. The reset signal erases all topological information stored on the node, even though the isochronous resources tend to remain the same during resets.

2. Tree Identification : The tree identification process defines the bus topology. Following a reset process and before the tree identification process is initialized, the bus has a flat logical topology, which directly represents the physical topology. At the end of the tree identification phase, a single node will be selected as the root node and the logical topology of the bus will be a tree. The example that follows demonstrates how the tree identification process is applied.

Suppose that 6 devices are connected as depicted on the following figure :

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki

Figure 6.

Devices A, B and C have only one connected port and are therefore characterised as leaf-nodes. Right after the reset signal, these nodes will send a Parent_Notify signal on their data and strobe lines. When an intermediate node receives this signal on one of its ports, then that port is marked as having a child and the signal Child_Notify is issued on that port's data and strobe lines. Upon the reception of this signal, the leaf-node marks his port as a parent port and stops the transmission of the Parent_Notify signal as an indication that the Child_Notify signal has been received. Bus state at this point is demonstrated on Figure 7.

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki

Figure 7.

At the end of the aformentioned process, the leaf-nodes have been identified, but the devices D and F still have a port that has not received a Parent_Notify signal. As a result, these devices will send this singal through their ports that haven't received it. The device E will receive the Parent_Notify on both its remaining ports (1 and 3) and will return the Child_Notify signal. This way, device E will mark all its ports as havign children and it will therefore become the root node.

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki

Figure 8.

Although not depicted in this specific example, at the end of the process more than one nodes could be candidates to become root-nodes. Should this happen, a random back-off timer is used to eventually settle on a root-node. A node may force itself to become a root-node by delaying its participation at the tree identification process for a while.

3. Self Identification : this process follows tree identification and consists of assigning physical IDs to each node of the bus, exchanging transmission speed capabilities between nodes and making each node aware of the bus topology that has been formed. The process starts from the root node by sending the Arbitration_Grant signal to lowest numbered port. At this point all nodes on the bus have a self ID counter set to zero. When an intermediate node receives the aformentioned singal, it forwards it to the lowest numbered port which is attached to a child -node. Eventually, the signal will be received by a leaf-node that can't forward it to any other node. This node will assign itself the physical ID 0 and will transmit upwards the self ID packet. The packet is transmitted to all network nodes, which upon reception increment their self ID counter. At this point, the leaf-node will send a self ID done signal, to inform its parent-node taht all nodes under it have completed the self ID procedure. The intermediate node will not forward this signal to the upper levels of the tree, unless all devices attached to its ports have completed the self ID procedure. When this happens, the node will assign itself the next physical ID and will propagate the self ID done signal to an upper level node. The latter will continue the process in a similar way and the self identification phase will terminate when the root-node receives the self ID done signal from all its ports. It will assign itself the next physical ID and therefore the root-node will become the device with the higher self ID number on the bus.

During the self ID process, neighboring nodes exchange data in the maximum data transfer speed that they can support. As a result, nodes are able to transmit at the maximum speed that is supported by the slowest device on path from sender to receiver.

Also, during the self ID process, all nodes willing to undertake the role of the Isochronous Resource Manager, will indicate this through the self ID packets that they transmit. The node with the higher physical ID that wishes to become an IRM, will eventually be granted this role.

At the physical layer, bus arbitration actions are also performed. All operations on the bus are synchronised using an 8kHz clock signal produced by the cycle master node. The cycle master node identifies with the root node of the network. Therefore, the clock period is 125μsec long and its structure is described on Figure 9.

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki

Figure 9.

Each cycle begins with the transmission of the cycle start packet from the cycle master. All devices on the bus use this packet to synchronise their respective clocks. Right after the transmission of the cycle start packet, the devices that wish to transmit isochronous packets may arbitrate for the bus. According to the arbitration scheme used on the 1394 standard, whenever a device wishes to gain access to the bus, it sends a signal to its parent-node, which in turn forwards it to the upper layers of the bus's tree structure, till it reaches the root node. The root node decides which node will gain access to the bus on a first come first serve basis. It becomes obvious that the device located closest to the root node wins the arbitration.

Each device that wishes to transmit isochronous packets is assigned a logic channel by the Isochronous Resource Manager. A channel may be used only once in every bus cycle. This ensures on one hand, that each device that has been granted a channel will transmit at some point during every cycle and on the other, that the devices located near the root node won't monopolize the bus. If a device has significant bandwidth requirements and there are available channels, then the IRM may grant this device more than one channels, enabling it to transmit multiple packets per clock cycle.

When the data of an isochronous channel have been streamed, the bus remains idle waiting for another isochronous channel to begin arbitration. If no other isochronous channel wishes to transmit data, the bus will remain idle for more time than the isochronous gap (the time interval between two isochronous transmissions with duration from 40 to 50 nsec). Should the bus idle time exceed the subaction gap, the devices that wish to transmit asychronous data may arbitrate for the bus. The arbitration scheme used for the asychronous transfers is the same as the one used for the isochronous ones.

The subaction or asychronous gap is the time interval between two asychronous subactions and it is greater in length than the isochronous gap. An asychronous subaction is defined as the transmission of an asychronous packet and the reception of the packet's acknowledgement.

In contrast to the isochronous transfers, for the asychronous transfers there is not a manager to assign transmission channels. As a result, the devices that wish to transmit multiple packets during the duration of a cycle, may arbitrate more than once for the bus. This may lead to unfairness for the devices that are located far from the root node, as the closest to the root devices are favoured. To alleviate this problem, the standard defines the fairness interval and the arbitration rest gap. The concept is simple. Each device that transmits asychronous packets has a bit named arbitration enable bit. Depending on the value of this bit, the device is entitled or not to arbitrate for the bus during the current cycle. Initially, the bit is set to 1 and when the device completes an asychronous transaction, it is cleared and the device may not participate in any arbitration process. This scheme ensures a fair access to the bus even for devices located far away from the root.

When all devices wishing access to the bus have been served, the bus will remain idle because all the arbitration enable bits are going to be zero and therefore no device will try to gain bus access. The bus idle time eventually will become greater than the subaction gap and as soon as it exceeds a value called arbitration rest gap, the devices may reset the arbitration enable bit and try to re-arbitrate for the bus.

The physical layer handles a few more operations than the ones described above. More specifically, when a device has no link layer implementation, then the physical layer acts as a repeater on the bus. Furthrmore, physical layer is responsible for the diagnosis of certain erroneous situations that may occur, such as the formation of cycles on the bus or power drops on the cable.

Link Layer

The link layer acts as the interface between the physical layer and the transaction layer. It handles the checking of the received CRCs (Cyclic Redundancy Code) as well as the computation and the addition of CRCs to transmitting packets. Since the transaction layer does not participate in the isochronous transfer process, the link layer is directly responsible for the transmission and reception of isochronous data. Lastly, at this layer packet header check is performed so as to determine the transaction type in process and to inform accordingly the upper layers.

At the IEEE 1394-1995 standard, the interface between the physical and link layer is not strictly defined. The revised specification of the standard (1394a), however, makes this interface part of the formal specs in order to deter any incompatibilities between ICs of different manufacturers.

The physical-link layer interface comprises of at least 17 signals that must be magnetically or capacitively isolated. The table that follows describes the most important of these signals :

Signal Source
LReqLink layerLink request - used to initialize a request for packet transmission, as well as a request for a direct access of a physical layer register
SClkPhysical layer49.152MHz clock used to synchronize data reads
Data[0:7]eitherData - data transfers are performed at a rate of 50Mbps, therefore the required lines depend on the supported speeds :
100Mbps - D[0:1]
200Mbps - D[0:3]
400Mbps - D[0:7]
These lines are also used by the physical layer to transfer status information to the link layer
Ctl[0:1]eitherControl interface - describes the interface status
LPSLink layerLink power status - it shows whether the link layer controller is powered
Link OnPhysical layerIt shows whether the physical layer is powered on so that the link layer controller may start functioning

In addition to these signals, there are a few more related to the specific implementation of the physical medium on a backplane.

As previously mentioned, the link layer assembles data received by upper layers into packets and sends them for transmission to the physical layer and reversely disassembles packets received from the physical layer and forwards their data to upper layers. Two types of packets are supported : isochronous and asychronous.

The form of an asychronous packets is shown on Figure 10.

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki
Figure 10.

A packet is split into two basic parts : the header and the payload. In the header information such as the transmitter and receiver addresses (Source_ID and Destination_ID respectively), the transaction code (tcode), the packet's priority (Pri) etc is contained. The actual data to be transmitted are located inside the payload. A CRC field for error checking is included in both header and payload.

Isochronous packets are simpler in structure. A typical isochronous packet is presented in Figure 11.
IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki

Figure 11.

In contrast to the asychronous packet, an isochronous packet does not include a destination address. The packet is simply placed on the bus in an isochronous channel and whichever node listens on that channel will receive the packet.
A typical implementation of the link layer provides an interface with the physical layer, a CRC generation and checking mechanism, FIFO (First-In First-Out) transmission and reception queues, interrupt registers, a host interface and at least one DMA channel. Manufacturers such as Texas Instruments, Philips, NEC, Sony and Fujitsu offer ICs implementing the link layer. Since the link layer handles isochronous packets, usually these ICs implement a few additional functions such as copyright protection, interfaces with A/V devices etc.

Transaction Layer

The transaction layer is used for the asychronous transfers. The protocol defines a request - response mechanism, with confirmations generated at each phase. Sevral types of transactions are allowed and they can be summed to the following :

  • simple 4-byte reads (4 bytes = 1 quadlet)
  • simple 4-byte writes
  • variable-length reads
  • variable-length writes
  • lock transactions

Lock transactions are used as a safe way to request bus resources from an administrative node. In principle, a node assumes that a resource (e.g. an isochronous channel) is available and sends a lock request packet for this resource. If the node's assumption is valid, then the resource is locked and no other node may arbitrate for it. The administrator node will allow the resource's lock only at the event that no other request for this resource is pending. That means that if the node's assumption about the availability of the resource is invalid, it will receive a lock response packet from the administrator node denying resource access.

Transactions may be split, concatenated, or unified. In the first case, a device that receives the transaction request cannot respond fast enough. So, when a request is received, the node will answer back with an acknoledgement packet. The bus automatically assigns bandwidth for acknoledgement packets and as a result a device does not need to arbitrate for bus access in order to transmit such a packet. During the time interval that a device processes a request, the bus may be used by other devices. When a respond is ready, the device has to arbitrate for bus access. When the response is sent, it will be read by the node that made the initial request and that node will also reply with an acknoledgement packet.

At the event that a node is fast enough, the whole process may be concatenated. That means that right after the transmission of the acknoledgement packet, the node may transmit the response packet without requiring to go through the arbitration phase to gain bus access.

The last transaction type - unified transaction - is only used during write transactions, when the receiving node may fulfill the write request imminently. The acknoledgement packet at this case includes a special code that is used as a response to the transmitter node that the write operation has been completed. This type of transactions cannot be applied to read and lock transactions since the acknoledgement packet is allowed to carry data.

The following Figure (Figure 12) presents graphically the three types of transactions :

IEEE 1394 (Firewire) High Speed Serial Bus - Tom's Wiki

Figure 12.

For the asychronous transactions, the 1394a specification adds 3 more bus arbitration types to maximize performance. The first type is named acknoledged accelerated arbitration. When a replying node has a request packet to send, then it may transmit it right after the acknoledgement packet without needing to arbitrate for the bus in advance.

The second type is called Fly-by arbitration and is applied to both isochronous and asychronous packets that need no confirmation (acknoledgement packets). It is used by nodes that have many ports and therefore act as repeaters. Such a node, may concatenate a similar speed packet with the one it transmits during its forwarding towards the root. Packets that can be concatenated are only those that need no confirmation and it matters not if they are of different types (isochronous - asychronous).

Finally, there is the token style arbitration. The application of this method requires a group of cooperating nodes. When the node of this group that is located closest to the root, gains access to the bus, it may grant access to the node of the group located furthest from the root. That node may then send a regular packet and all other nodes of the group can use fly-by arbitration to concatenate their own packets to the one initially sent as it travels the bus towards the root.

Bus Management

The management of a 1394 bus involves a number of different tasks that may be distributed among numerous nodes. The nodes on the bus premise the existance of a cycle master, an isochronous resource manager and a bus manager. Just like the transaction layer, the fuanctionality of this layer is also implemented in software.

The cycle master is the node that initiates the 125μsec cycles. The cycle master must be the root node and at the event that a node which cannot act as a cycle master becomes the root node, the bus is reset and a cycle master capable node is forced to become the root. The cycle master initiates a new bus cycle by sending a cycle start packet every 125μsec. This time may be violated if an asychronous transaction is not completed. If this happens, the start of the cycle is delayed and the cycle master includes in the cycle start packet the amount of time of this delay.

After a bus reset, all nodes wishing to transmit isochronous packets must obtain a channel and secure a certain amount of bandwidth. The role of the Isochronous Resourc Manager (IRM) is to manage this information. Two registers in the IRM are used to store it and are named Bandiwdth Available and Channels Available. The distribution of channels is realised through the Channels Available register. It has a width of 64 bits and each bit represents a channel. If the value of a bit in the register is 1, that means that the corresponding channel is available. A node that requests an isochronous channel, sets the first available bit at the value 0 and uses the bit position as its Channel_ID. Furthermore, the node must also check the Bandwidth Available register to find out the amount of bandwidth it may allocate. The bandwidth is measured through allocation units and each allocation unit represents the time required to transmit 4 bytes in a 1600Mbps speed. Total bandwidth is 6144 allocation units and if there are devices on the bus that want to transmit asychronous data, then the bandwidth reserved for isochronous transfers is restricted to 4915 allocation units. The nodes that wish to use an amount of the available bandwidth must subtract the amount required from the Bandwidth Available register.

The bus manager has to perform a number of tasks, which involve the announcement of the bus logical topology and the speed characteristics to the nodes, the power management and the optimization of traffic on the bus. Logical topology of the bus may be used by nodes to provide through an "intelligent" user interface notifications and suggestions to a user on how to set up the network to achieve maximum throughput among the nodes. The information concerning speed characteristics is used by the nodes to determine the speed that they can communicate with each other.

Also, the bus manager is responsible to determine whether the selected root node is cycle master capable. If it is not, then the bus manager seeks a capable node and then triggers a bus reset in order to cause that node to be selected as the root. Should no capable node be discovered, a number of the root node functions is assigned to the IRM.


Apple, the company behind the Macintosh personal computer platform, was the inventor of the 1394 bus and therefore its operating system (MacOS) has integrated support for this standard since its early appearence. Windows-based PCs have started to offer support for 1394 through the newer Windows Driver Model (WDM) used at the latest iterations of these OSes. Microsoft in collaboration with companies supporting the 1394 standard have developped the spec 1394 Open Host Controller Interface (OHCI). The spec provides for a link layer controller as well as bus management functionality and in general a certain implementation structure so that a standard driver provided by Microsoft may be use the controller and schedule transfers.

Furthermore, Microsoft provides WDM streaming drivers to support audio / video devices such as DVD players, tuners, MPEG decoders and audio codecs. For storage devices, printers and scanners the SBP-2 protocol (Serial Block Protocol) is supported. Beyond these protocols, depending on the device that uses 1394 connectivity, other protocols have been or are currently being developped. One may mention as examples the DV (Digital Video) and DPP (Direct Print Protocol) standards.

A lot of companies have also developped 1394 protocol stacks for embedded systems. The characteristic of most implementations of this category is that they are OS independent.

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